Job Description

Acara Solutions has been providing advanced manufacturing and technology firms our staffing related services since the 1950's. Our low power wireless technology client is looking for a Principle SoC Full-Chip Implementation and Verification Engineer to join their organization as a direct salaried employee in either their San Diego or San Jose offices. The base salary target is $220K with possible flexibility up to $240K.

The key qualifications for this principle physical design engineer covers:

• Full chip floor planning, bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SOC implementation and verification flow from RTL-to-GDS that includes full chip floor plan, place and route, CTS, and layout verification sign off on lower power SoC.

The term RTL-to-GDS refers to the entire implementation flow that transforms a digital design described in RTL (Register Transfer Level) into a GDS (Graphic Data System) file — the final physical layout file sent to the semiconductor foundry for chip fabrication. This is the full SoC physical design flow , and it's central to what many principal-level SoC engineers are responsible for managing or guiding.

We are seeking a highly experienced and innovative engineer to lead the full-chip implementation and verification of complex System-on-Chip (SoC) designs. This role involves overseeing the end-to-end process from RTL development through to post-silicon validation, ensuring the delivery of high-performance, reliable, and power-efficient SoCs.

Required Skills / Qualifications:

BSEE or MSEE and PhD a plus

Min 10 years of SoC physical design and verification that includes the above experience in bold

Preferred:

Wireless low-power experience

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